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L9733
Octal self configuring Low/High side driver
Preliminary Data
Features

Eight independently self configuring low/high drivers Supply voltage from 4.5V to 5.5V RON(max)=0.7 @ Tj = 25C, RON(max)=1.2 @Tj = 125C Minimum current limit of each output 1A Output voltage clamping min. 40V in low side configuration Output voltage clamping max. -14V in high side configuration SPI interface for outputs control and for diagnosis data communication Additional PWM inputs for 3 outputs Independent thermal shutdown for all outputs Open load, Short to GND, short to Vb, Overcurrent diagnostics in latched or unlatched mode for each channel Internal charge pump without need of external capacitor Controlled SR for reduced EMC Outputs 1-8 are self-configuring as high or low side drives. Self-configuration allows a user to connect a high or low side load to any of these outputs and the L9733 will drive them correctly as well as provide proper fault mode operation with no other needed inputs. In additon, Outputs 6, 7 and 8 can be PWM controlled via a external pins (IN6-8). This device is capable of switching variable load currents over the ambient range of -40C to +125C. The outputs are MOSFET drivers to minimize Vdd current requirements. For low side configured outputs an internal zener clamp from the drain to gate with a breakdown of 50V minimum will provide fast turn off of inductive loads. When a high side configured output is commanded OFF after having been commanded ON, the source voltage will go to (VGND - 15V). An 16 bit SPI input is used to command the 8 output drivers either "On" or "Off", reducing the I/O port requirement of the microcontroller. Multiple L9733 can be daisy-chained. In addition the SPI output indicates latched fault conditions that may have occurred. SO-28 PowerSSO-28

Description
The L9733 IC is a highly flexible monolithic, medium current, output driver that incorporates 8 outputs that can be used as either internal low or high side drives in any combination.
Order codes
Part number L9733 L9733XP Package SO-28 PowerSSO-28 (Exposed pad) Packing Tube Tube
August 2006
Rev 3
1/33
www.st.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
L9733
Contents
1 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute maximun ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Electrical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 3.3 DC Characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 AC Characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SPI Characteristics and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Configurations for Outputs 1-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.1 4.1.2 Low Side Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 High Side Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 4.3 4.4 4.5
Outputs 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Outputs 6-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Drn1-8 Susceptibility To Negative Voltage Transients . . . . . . . . . . . . . . . 18 Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5.1 4.5.2 4.5.3 Main Power Input (Vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Battery supply (Vbat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Discrete Inputs Voltage Supply (VDO) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6
Discrete inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6.1 4.6.2 Output 6-8 Enable Input (In6, ln7, ln8) . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reset Input (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 5.2 5.3 5.4 5.5 5.6 Serial Data Output (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Serial Data Input (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Chip Select (CS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Initial Input Command Register & Fault Register SPI Cycle . . . . . . . . . . . 21 Input Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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L9733
Contents
6
Other L9733 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 6.2 6.3 6.4 Charge Pump Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Waveshaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 POR Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7
Fault Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 Low Side Configured Output Fault Operation . . . . . . . . . . . . . . . . . . . . . . 24
7.1.1 7.1.2 No latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2
High Side Configured Output Fault Operation . . . . . . . . . . . . . . . . . . . . . 26
7.2.1 7.2.2 No latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 9
Package informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/33
List of tables
L9733
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute maximun ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SPI Characteristics and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bit Command Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Command Register Logic Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Fault Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Fault Logic Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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L9733
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Pin Connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output Turn On/Off Delays and Slew Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DO Loading for Disable Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI Input/Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 L9733 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 L9733 HVAC applicative examplesL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 L9733 Powertrain applicative examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SO28 Mechanical Data & Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PowerSSO28 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5/33
Pin description
L9733
1
Pin description
Figure 1. Pin Connection (Top view)
VDD SCLK CS SRC1 DRN1 DRN2 SRC2 SRC3 DRN3 DRN4 SRC4 IN6 IN7 Vbat 1 2 3 4 5 6 7 8 9 10 11 12 13 14
D06AT544
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDO D0 D1 SRC8 DRN8 DRN7 SRC7 SRC6 DRN6 DRN5 SRC5 RES IN8 GND
Table 1.
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Pin Description
Pin VDD SCLK CS SRC1 DRN1 DRN2 SRC2 SRC3 DRN3 DRN4 SRC4 IN6 IN7 Vbat GND IN8 RES SRC5 5 Volt Supply Input SPI Serial Clock Input SPI Chip Select (Active Low) Source Pin of Configurable Driver #1 (0.7 Rdson @+25) Drain Pin of Configurable Driver #1(0.7 Rdson @+25) Drain Pin of Configurable Driver #2 (0.7 Rdson @+25) Source Pin of Configurable Driver #2 (0.7 Rdson @+25) Source Pin of Configurable Driver #3 (0.7 Rdson @+25) Drain Pin of Configurable Driver #3 (0.7 Rdson @+25) Drain Pin of Configurable Driver #4 (0.7 Rdson @+25) Source Pin of Configurable Driver #4 (0.7 Rdson @+25) Discrete Input used to PWM Output Driver #6 Discrete Input used to PWM Output Driver #7 Battery Supply Voltage Analog Ground Discrete Input used to PWM Output Driver #8 Reset Input (Active Low) Source Pin of Configurable Driver #5 (0.7 Rdson @+25) Function
6/33
L9733 Table 1.
N 19 20 21 22 23 24 25 26 27 28
Pin description Pin Description (continued)
Pin DRN5 DRN6 SRC6 SRC7 DRN7 DRN8 SRC8 DI DO VDO Function Drain Pin of Configurable Driver #5 (0.7 Rdson @+25) Drain Pin of Configurable Driver #6 (0.7 Rdson @+25) Source Pin of Configurable Driver #6 (0.7 Rdson @+25) Source Pin of Configurable Driver #7 (0.7 Rdson @+25) Drain Pin of Low Side Driver #7 (0.7 Rdson @+25) Drain Pin of Low Side Driver #8 (0.7 Rdson @+25) Source Pin of Configurable Driver #8 (0.7 Rdson @+25) SPI Data In SPI Data Out Microcontroller Logic Interface Voltage
7/33
Operating conditions
L9733
2
2.1
Operating conditions
Maximum ratings
This part may not operate if taken outside the maximum ratings. Once the condition is returned to within the specified maximum rating or the power is recycled, the part will recover with no damage or degradation. Table 2.
Symbol Vdd Vbat Tj Supply Voltage Battery Supply Voltage Thermal Junction Temperature Range Snubbing Volatage of DRN1-8 IO Output Current 1-8
Maximum ratings
Parameter Value 4.5 to 5.5 4.5 to 18 -40 to 150 min 50 max 800 Unit V V C VDC mA
2.2
Absolute maximun ratings
This part may be irreparably damaged if taken outside the specified Absolute Maximum Ratings. Operation outside the Absolute Maximum Ratings may also cause a decrease in reliability. Table 3.
Symbol VDD Vbat Supply Voltage Supply Voltage CS,DI,DO,SCLK,EN,IN6,IN7,IN8,VDO SRC 1-8 DRN1-8 IOL IOP Current Limit of Output 1-8 ( -40C) OverCurrent protection at Output 1-8 ( -40C) Maximum Clamping Energy ESD Human Body Model
Absolute maximun ratings
Parameter Value -0.3 to 7 -0.3 to 40 -0.3 to 7.0 -24 to 40 -0.3 to 60 2.5 3 20 2 vs. GND Unit V V V VDC VDC A A mj kV
Table 4.
Symbol Tamb Tstg Tj Rth
Thermal Data
Parameter Operating Ambient Temperature StorageTemperature Maximum Operating Junction Temperature Thermal Shut-down Temperature 151 175 Min -40 -50 Typ Max 125 150 150 200 Unit C C C C
8/33
L9733 Table 4.
Symbol Rth-hys RTh j-amb RTh j-case RTh j-pins
Operating conditions Thermal Data
Parameter Thermal Shut-down Temperature Hysteresis Thermal resistance junction to ambient for SO28 (1) for PowerSSO28 (2) Thermal resistance junction to case (PowerSSO28) Thermal resistance junction to pins (SO28) Min 7 Typ 10 Max 25 55 24 3 20 Unit C C/W C/W C/W C/W
1. With 6cm2 on board heat sink area. 2. With 2s2p PCB thermally enhanced.
9/33
Electrical performance characteristics
L9733
3
Electrical performance characteristics
These are the electrical capabilities this part was designed to meet. It is required that every part meet these characteristics.
3.1
DC Characteristics:
Tamb = -40 to 125C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18Vdc (high side configuration), unless otherwise specified.
Table 5.
Symbol IN6vih IN6vil IIN6il IIN6ih IN7vih IN7vil IIN7il IIN7ih IN8vih IN8vil IIN8il IIN8ih CSih CSil ICSih ICSil SCLKih SCLKil ISCLKih ISCLKil DIih DIil IDIih IDIil DOol DOoh
DC Characteristics
Parameter IN6 Input Voltage 0.3vdo In6 = 0 VDC IN6 Input Current In6 = VDO IN7 Input Voltage Voltage 0.3vdo In7 = 0 VDC IN7 Input Current In7 = VDO IN8 Input Voltage 0.3vdo In8 = 0 VDC IN8 Input Current In8 = VDO CS Input Voltage 0.3vdo CS = VDO CS Input Current CS = 0 VDC SCLK Input Voltage 0.3vdo SCLK = VDO SCLK Input Current SCLK = 0 VDC DI Input Voltage 0.3vdo DI = VDO DI Input Current DI = 0 VDC DO Output Voltages IDO = 2.5 mA IDO = -2.5 mA vdo-0.6 10 100 0.4 |10| V A A V V 10 100 0.7vdo |10| V A A V 10 100 0.7vdo |10| V A A V 10 100 0.7vdo |10| V A A V 10 100 0.7vdo |10| V A A V 10 100 0.7vdo |10| V A A V Conditions Min Typ Max 0.7vdo Units V
10/33
L9733 Table 5.
Symbol Symbol IDOzol IDOzoh RESih RESil IRESil IRESih RES = 0 VDC RES Input Current RES = VDO RES Input Voltage
Electrical performance characteristics DC Characteristics (continued)
Parameter Parameter DO Tri-State Currents DO = VDO |10| 0.7vdo 0.3vdo 10 100 |10| Conditions DO = 0 VDC Conditions Min Min Typ Typ Max Max |10| Units Units A A V V A A
Islp
Vbat Sleep Current
VDD = SRC1-8 = 0VDC DRN1-DRN8=18VDC , Vb. Sum currents(Tamb > 0C) (Tamb @ -40C) VDD=5V All Outputs Commanded On All Outputs Commanded On All Outputs Commanded Off VDD = 0 VDC : SRC1-8 = 0 VDC DRN1- DRN8 = 16 VDC DRN1- DRN8 = 40 VDC VDD = 0 VDC : SRC1-8 = 0 VDC DRN1- 8 = 16 V DRN1- 8 = 40 VDC SRC1-8 = GND DI = AC00h Rload 11K Rload 200K VBAT>=9V DRN1-DRN8 = GND 10 120 11 -10 10 -18 2.7 0.5
10 3 15 8.5
A A mA mA mA
Ivbat IVDD IVDD IDRN1lk IDRN8lk ISRC1lk ISRC8lk.
Vbat current Max VDD Current Min VDD Current DRN1 - DRN8 Leakage Currents (Low Side) SRC1 - SRC8 Leakage Currents (High Side) DRN1 - DRN8 Sink Current (Low Side) Open Load Detection Resistance
5 10 -5 -10 100 280 200 -100 100 -100 3.1
A A A A A A K A A A V
IDrn1-8sink
RDRN1-8
IDrn1-8source Source Current Isrc1-8sink Isrc1-8source
DRN1- 8 = Vb, DI = AC00h SRC1 - SRC8 Sink/Source SCR1- 8 = Vb Current High Side) SCR1- 8 = GND SRC1- 8 = GND, DI = AC00h DRN1- DRN8 = Open Vdd=4.9 to 5.1 Vdc SRC1- 8 = GND, DI = AC00h DRN1- DRN8 = Open
VDrn1-8open
DRN1 - DRN8 Open Load Voltage (Low Side)
2.5
3.5
V
Vsrc1-8open
SRC1 - SRC8 Open Load DRN1-8 = Vb, DI = AC00h Voltage (High Side) DRN1 SCR1-8 = open DRN8
2.0
2.8
V
11/33
Electrical performance characteristics Table 5.
Symbol
L9733
DC Characteristics (continued)
Parameter Conditions DI = ACFFh, DI = AAFFh SRC1 - SRC8 = 0 VDC DRN1 - DRN8 = 4.5 - 16 VDC (Tamb > 0C) (Tamb @ -40C ) Conditions DI = AC00h, DI = AA00h SRC1 - SRC8 = 0 VDC DRN1 - DRN8 = 4.5 - 16 VDC (Tamb > 0C) (Tamb - 40C) DI = ACFFh, DI = AAFFh DRN1 - DRN8 = Vb SRC1 - SRC8 = GND (Tamb > 0C) (Tamb - 40C) DI = AC00h, DI = AA00h DRN1 - DRN8 = Vbat SRC1 - SRC8 = GND (Tamb > 0C) (Tamb - 40C) Min Typ Max Units
IDRN1limit IDRN8limit
DRN1 - DRN8 Current Limits (Low Side)
1 1 Min Typ
2.2 2.5 Max
A A Units
Symbol
Parameter
IDRN1OVCIDRN8OVC
DRN1 - DRN8 Overcurrent threshold (Low Side)
1 1
2.7 3
A A
ISRC1limitISRC8limit
SRC1 - SRC8 Current Limits (High Side)
1 1
2.2 2.5
A A
SRC1 - SRC8 Overcurrent threshold (High Side) DRN1 - DRN8 DRN1Cl+ DRN8Cl+ SRC1Cl+SRC8Cl+
ISRC1OVCISRC8OVC
1 1
2.7 3
A A
DRN1 - DRN8 DI = AC00h Clamp Voltages (Low Side) SRC1-8 = GND, IDRN1-8 = 350 mA SRC1 - SRC8 DI = AC00h Clamp Voltages (High Side) DRN1-8 = Vbat, ISRC1-8 = -350 mA DRN1 - DRN8 DI = AC00h SRC1 - SRC8 = GND: Decrease Drn1 - Drn8 until Faults are "Set" DI = AC00h SRC1 - SRC8 = GND : Increase Drn1 - Drn8 until Faults are "Not Set" DI = AC00h Drn1 - Drn8 = Vb: Decrease SRC1 - SRC8 until Faults are "Not Set" DI = AC00h Drn1 - Drn8 = Vbat: Increase SCR1 - SCR8 until Faults are " Set"
50 -24
60 -14
V V
VDrn1-8open - DRN18VthGND DRN18VthVbatVDrn1-8open VDrn1-8open - SRC18VthGND SRC18VthVbatVDrn1-8open
Short to GND threshold distance from open load voltage (Low side) DRN1 - DRN8 Short to Vbat threshold distance from open load voltage (Low Side) SRC1 - SRC8 Short to GND threshold distance from open load voltage (High Side) SRC1 - SRC8 Short to Vbat threshold distance from open load voltage (High Side)
0.3
0.7
V
0.3
0.7
V
0.2
0.6
V
0.2
0.6
V
12/33
L9733 Table 5.
Symbol
Electrical performance characteristics DC Characteristics (continued)
Parameter Conditions @ +125C @ IDRN = 350mA Min Typ Max 1.2 0.7 0.5 Units W W W
On Resistance RdsonDrn1-8 (Drn to SRC1-8)
@ +25o C @ IDRN = 350mA @ -40C @ IDRN = 350mA
Drn1-8ther
(1)
Thermal Shutdown Temperature
DI = ACFFh, IDrn1-8 = 1 mA, SRC1 - SRC8 = GND, Increase temperature until Drn1 - Drn8 > 2 VDC, Verify DO Bits 0-15 are "Set" Drn1 - Drn8 < 2 VDC
151
200
C
Drn1-8hyst(1) Hysteresis
1. Design Information, Not Tested.
5
15
C
3.2
Table 6.
Symbol
AC Characteristics:
Tamb= -40 to 125C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18Vdc, unless otherwise specified AC Characteristics
Parameter DRN1 - DRN8 Open load & short to GND filter time (Low Side) (Latch mode) SRC1 - SRC8 Open load & short to Vbatfilter time (High Side) (Latch mode) DRN1 - DRN8 Overcurrent Switch Off Delay (Low Side) SRC1 - SRC8 Overcurrent Switch Off Delay (High Side) Restart time after overcurrent switch off Time (Int) Slew Rate Turn On Turn Off (Low Side) Conditions Min Typ Max Units
TfiltDRN1-8
DI = AC00h, DI = A3FFh SRC1 - SRC8 = GND
300
900
s
TfiltSRC1-8
DI = AC00h, DI = A3FFh DRN1 - DRN8 = Vb
300
900
s
TdelDRN1-8
DI = ACFFh, DI = AA00h SRC1 - SRC8 = GND
10
60
s
TdelSRC1-8
DI = ACFFh, DI = AA00h DRN1 - DRN8 = Vb
10
60
s
Tres
DI = ACFFh, DI = AA00h Outputs loaded per Figure 5 See Figure 2 See Figure 2
120
450
ms
Drn1-8htol Drn1-8ltoh
0.65 0.5
1.95 1.5
V/s V/s
13/33
Electrical performance characteristics Table 6.
Symbol SRC1-8htol SRC1-8ltoh Drn1-8tondly Drn1-8toffdly SRC1-8tondly
L9733
AC Characteristics (continued)
Parameter Slew Rate Turn On Turn Off (High Side) Delay time Turn On Turn Off (Low Side) Delay time Turn On Conditions Outputs loaded per Figure 5 See Figure 2 See Figure 2 Outputs loaded per Figure 5 See Figure 2 See Figure 2 Outputs loaded per Figure 5 See Figure 2 See Figure 2 Drn1-8toffdly - Drn1-8tondly SRC1-8toffdly - SRC1-8tondly Min Typ Max Units
0.65 0.5
1.95 1.5
V/s V/s
2 10 Figure 2 2 10 10 10
20 100
s s
20 100 60 60
s s s s
SRC1-8toffdly Turn Off (High Side) Drn1-8offon SRC1-8offon Delay Delta Delay Delta
Figure 2.
Output Turn On/Off Delays and Slew Rates
IN 6- 8
90% 20%
IN 6-8 90%
LSD
DRN1-8
DRN1-8htol DRN1-8tondly
DRN1-8 20%
DRN1-8ltoh DRN1-8toffdly
HSD
SRC1-8
SRC1-8ltoh SRC1-8tondly
80% 10%
80%
SRC1-8
SRC1-8htol SRC1-8toffdly
10%
IN1- 5 are available on wafer on ly
14/33
L9733
Electrical performance characteristics
3.3
Table 7.
Symbol DINCin SCLKCin DOrise DOfall DOa DOsum DOhm DOdis tthFilt SCLKwid SCLKlm SCLKhm SCLKrise SCLKfall CSrise CSfall CSlead CSlag DIrise DIfall DIsus DIhs
SPI Characteristics and timings
Tamb= -40 to 125C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18Vdc, unless otherwise specified SPI Characteristics and timings
Parameter Input Capacitance 20 Output Data (DO) Rise Time Output Data (DO) Fall Time Access Time Set Up Time Hold Time Output Data (DO) Disable Time Filter Time SCLK Width SCLK Low Time SCLK High Time SCLK Rise Time SCLK Fall Time Channel Select (CS) Rise Time Channel Select (CS) Fall Time Channel Select (CS) Lead Time Channel Select (CS) Lag Time Input Data (DI) Rise Time Input Data (DI) Fall Time Input Data (DI) Set-up Time Input Data (DI) Hold Time 50 pF from DO to Ground See Figure 4 See Figure 4 See Figure 5 See Figure 5 See Figure 5 No Capacitor on DO, See Figure 4 All Fault bits are "Set" See Figure 4, @ fSCLK = See Figure 4, @ fSCLK = 5.4MHz(1) 5.4MHz(1) 5 185 58 58 21 21 100 100 165 50 30 30 15 10 ns ns 20 10 400 20 Figure 5 70 70 350 pF ns ns ns ns ns ns s ns ns ns ns ns ns ns Conditions Min Typ Max 20 Units pF
See Figure 4, @ fSCLK = 5.4MHz(1) See Figure 4, @ fSCLK = See Figure 4, @ fSCLK = See Figure 4(1) See Figure 4(1) See Figure 5(1) See Figure 5(1) See Figure 4, @ fSCLK = 5.4MHz(1) See Figure 4, 5, @ fSCLK = 5.4MHz(1) See Figure 5, @ fSCLK = 5.4MHz(1) See Figure 5, @ fSCLK = 5.4MHz(1) 5.4MHz(1) 5.4MHz(1)
1. Guaranteed by design
15/33
Electrical performance characteristics Figure 3. DO Loading for Disable Time Measurement
Vcc +5 V 4.0 V 1k DOdis DO
L9733
DO 0V 1k CS
1.0 V
Figure 4.
SPI Input/Output Slew Rate
SCLKwid
SCLKlm
90%
SCLKhm
SCLKrise
10%
SCLK
90%
SCLKfall DI
90%
CSrise
CS
10%
CSfall
DIrise
10%
DIfall
DOrise
10%
90%
DO
DOfall
Figure 5.
SPI Timing Diagram
CS
CSlead CSlag
SCLK
DOa DOsum FAULT LSB
DOhm FAULT MSB DI
DOdis
DO
DI LSB DIsus DIhs
DI MSB
DI
16/33
L9733
Functional description
4
Functional description
L9733 integrates 8 self-configuring outputs (OUT1-8) which are able to drive either incandescent lamps, inductive loads (non-pwm'd, in pwm is necessary an external diode to reduce flyback power dissipation), or resistive loads biased to Vbat ( low side configuration) or to GND (high side configuration). These outputs can be enabled and disabled via the SPI bus. Each of these outputs has a short circuit protection (with 0.8-2.4 Amps threshold) selectable via SPI bus between a filtered switching OFF overcurrent protection or a linear current limitation (default condition after power ON is switching OFF protection enabled). An over-temperature protection as described in Section 2.1 is available for each outputs. When a high side configured output is commanded OFF after having been commanded ON, the source voltage will go to (VGND - 15V). This is due to the design of the circuitry and the transconductance of the MOSFET. When a low side configured output is commanded OFF after having been commanded ON, the output voltage will rise to the internal zener clamp voltage (50 VDC minimum) due to the flyback of the inductive load. Outputs 1-8 are able to drive any combination of inductive loads or lamps at one time. Inductive loads for the L9733 can range from 35mH to a maximum of 325mH. The recommended worst-case solenoid loads (at -40C) are calculated using a minimum resistance of 40 for each output. The maximum single pulse inductive load energy the L9733 outputs is able to be safely handle is 20mJ at -40C to 125C (Worst-case load of 325mH & 40).
4.1
Configurations for Outputs 1-8
The drain and source pins for each Output must be connected in one of the two following configurations (see Figure 6).
4.1.1
Low Side Drivers
When any combination of Outputs 1-8 are connected in a low side drive configuration the source of the applicable Output (Src1-8) shall be connected to ground. The drain of the applicable Output (Drn1-8) shall be connected to the low side of the load.
4.1.2
High Side Drivers
When any combination of Outputs 1-8 are connected in a high side drive configuration the Drain of the applicable Output (Drn1-8) shall be connected to Vbat. The source of the applicable Output (Src1-8) shall be connected to the high side of the load.
4.2
Outputs 1-5
These five outputs can be used as either high or low side drives. The room temperature Rdson of these outputs is 0.7. A current limited (100A max) voltage generator is connected to Src 1-5 for open load and short to GND detection when a low side configured output is commanded OFF. Another current limited (100A max if VDrn 1-5 > 60%Vbat, 280A max if VDrn 1-5 < 60%Vbat) voltage generator is connected to Drn 1-5 for open load and short to Vbat detection when a high side configured output is commanded OFF. Drain pins of Outputs 1-5 (Drn1-5) are connected to the drains of the N channel MOSFET
17/33
Functional description
L9733
transistors. Source pins of Outputs 1-5 (Src1-5) are connected to the sources of the N channel MOSFET transistors.
4.3
Outputs 6-8
These three self-configuring outputs can be used to drive either high or low side loads. In addition to being controlled by the SPI BUS these outputs can also be enabled and disabled via the IN6 & IN7& IN8 inputs. The IN6, IN7 and IN8 inputs are logically or'd with the SPI commands to allow either the IN6 & IN7 & IN8 inputs or the SPI commands to activate these outputs. The use of the IN6 & IN7 & IN8 pins for PWM control on these outputs should only be done with non-inductive loads if an external flyback diode is not present. The room temperature Rdson of these four outputs is 0.7. A current limited (100A max) voltage generator is connected to Src 6-8 for open load and short to GND detection when a low side configured output is commanded OFF. Another current limited (100A max if VDrn 6-8 > 60%Vbat, 280A max if VDrn 6-8 < 60%Vbat) voltage generator is connected to Drn 6-8 for open load and short to Vbat detection when a high side configured output is commanded OFF. Drain pins of Outputs 6-8 (Drn6-8) are connected to the drains of the N channel MOSFET transistors. Source pins of Outputs 6-8 (Src6-8) are connected to the sources of the N channel MOSFET transistors.
4.4
Drn1-8 Susceptibility To Negative Voltage Transients
All outputs connected in the low side configuration must have a ceramic chip capacitor of 0.01F to 0.1F connected from drain to ground. This is needed to prevent potential problems with the device operation due to the presence of fast negative transient(s) on the drain(s) of the device. Adequate de-coupling capacitors from the Drain (VBAT) to ground shall be provided for high side configured outputs.
4.5
4.5.1
Supply pins
Main Power Input (Vdd)
An external +5.0 0.5 VDC supply provided from an external source is the primary power source to the L9733. This supply is used as the power source for all of its internal logic circuitry and other miscellaneous functions.
4.5.2
Battery supply (Vbat)
This input is the supply for the on board charge pump. This input shall be connected directly to battery. If this input is not connected to the same supply, without additional voltage drops, of the drains of any high side connected outputs, then the Rdson of that given output will be higher than the specified maximum.
4.5.3
Discrete Inputs Voltage Supply (VDO)
This pin is used to supply the discrete input stages of L9733 and must be connected to the same voltage used to supply the peripherals of the processor interfaced to L9733.
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L9733
Functional description
4.6
4.6.1
Discrete inputs
Output 6-8 Enable Input (In6, ln7, ln8)
This input allows Output 6 (or Output 7, or Output 8) to be enabled via this external pin without the use of the SPI. The SPI command and the In6-7 input are logically or'd together. A logic "1" on this input (In6, ln7 or ln8) will enable this output no matter what the status of the SPI command register. A logic "0" on this input will disable this output if the SPI command register is not commanding this output on. This pins (In6, ln7 or ln8) can be left "open" if the internal output device is being controlled only via the SPI. This input has a nominal 100k resistor connected from this pin to ground, which will pull this pin to ground if an open circuit condition occur. This input is ideally suited for non-inductive loads that are pulse width modulated (PWM'd). This allows PWM control without the use of the SPI inputs.
4.6.2
Reset Input (RES)
When this input goes low it resets all the internal registers and switches off all the output stages. This input has a nominal 100 k resistor connected from this pin to VDD, which will pull this pin to VDD if an open circuit condition occur.
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Serial Peripheral Interface (SPI)
L9733
5
Serial Peripheral Interface (SPI)
The L9733 has a serial peripheral interface consisting of Serial Clock (SCLK), Data Out (DO), Data In (DI), and Chip Select (CS). All outputs will be controlled via the SPI. The input pins CS, SCLK, and DI, thanks to VDO pin, have level input voltages allowing proper operation from microcontrollers that are using 5.0 or 3.3 volts for their Vdd supply. The design of the L9733 allows a "daisy-chaining" of multiple L9733's to further reduce the need for controller pins.
5.1
Serial Data Output (DO)
This output pin is in a tri-state condition when CS is a logic '1'. When CS is a logic '0', this pin transmits 16 bits of data from the fault register to the digital controller. After the first 16 bits of DO fault data are transmitted (after a CS transition from a logic '1' to a logic '0'), then the DO output sequentially transmits the digital data that was just received (16 SCLK cycles earlier) on the DI pin. The DO output continues to transmit the 16 SCLK delayed bit data from the DI input until CS eventually transitions from a logic '0' to a logic '1'. DO data changes state 10 nsec or later, after the falling edge of SCLK. The LSB is the first bit of the byte transmitted on DO and the MSB is the last bit of the byte transmitted on DO, once CS transitions from a logic '1' to a logic '0'.
5.2
Serial Data Input (DI)
This input takes data from the digital controller while CS is low. The L9733 accepts an 16 bit byte to command the outputs on or off. The L9733 also serially wraps around the DI input bits to the DO output after the DO output transmits its 16 fault flag bits. The LSB is the first bit of each byte received on DI and the MSB is the last bit of each byte received on DI, once CS transitions from a logic '1' to a logic '0'. The last 4 bits (b15-b12) of the first 16 bit byte are used as key-word. The 4 bits (b11-b8) of the first 16 bits byte are used to select writing mode between OUT8-1 status and diagnosis operating mode . The DI input has a nominal 100 k resistor connected from this pin to the VDO pin, which pulls this pin to VDO if an open circuit condition occurs.
5.3
Chip Select (CS)
This is the chip select input pin. On the falling edge of CS, the DO pin is released from tristate mode. While CS is low, register data are shifted in and shifted out the DI pin and DO pin, respectively, on each subsequent SCLK. On the rising edge of CS, the DO pin is tristated and the fault register is "Cleared" if a valid DI byte has been received. A valid DI byte is defined as such: - - 1 A multiple of 16 bits was received. 2 A valid key-word was received
The fault data is not cleared unless all of the 2 previous conditions have been met. The CS input has a nominal 100k resistor connected from this pin to the VDO pin, which pulls this pin to VDO if an open circuit condition occurs.
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L9733
Serial Peripheral Interface (SPI)
5.4
Serial Clock (SCLK)
This is the clock signal input for synchronization of serial data transfer. DI data is shifted into the DI input on the rising edge of SCLK and DO data changes on the falling edge of SCLK. The SCLK input has a nominal 100k resistor connected from this pin to the VDO pin, which pulls this pin to VDO if an open circuit condition occurs.
5.5
Initial Input Command Register & Fault Register SPI Cycle
After initial application of Vdd to the L9733, the input command register and the fault register are "Cleared" by the POR circuitry and that means that the default condition for the output status is Off , the default diagnostic mode is No Latch and the switching OFF overcurrent protection is enable. During the initial SPI cycle, and all subsequent cycles, valid fault data will be clocked out of DO (fault bits).
5.6
Input Command Register
An input byte (16 bits) is routed to the Command Register. The content of this Command Register is given in table 9. Additional DI data will continue to be wrapped around to the DO pin. If CS should happen to go high before complete reception of the current byte, this just transmitted byte shall be ignored (invalid).
Table 8.
Bit Command Register Definition
Key Word Writing Mode: Output Output Status LSB 0 1 b13 0 b12 1 b11 1 b10 0 b9 0 b8 OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1 b7 b6 b5 b4 b3 b2 b1 b0
MSB 1 b15
b14
Key Word MSB 1 b15 0 b14 1 b13 0 b12
Writing Mode: Diag
Driver Diag Mode LSB
0 b11
0 b10
1 b9
1 b8
Diag 8 Diag 7 Diag 6 Diag 5 Diag 4 Diag 3 Diag 2 Diag 1 b7 b6 b5 b4 b3 b2 b1 b0
Key Word MSB 1 b15 0 b14 1 b13 0 b12
Writing Mode: Protect
Driver Overcurrent Protection LSB
1 b11
0 b10
1 b9
0 b8
Ilim 8 Ilim 7 Ilim 6 Ilim 5 Ilim 4 Ilim 3 Ilim 2 b7 b6 b5 b4 b3 b2 b1
Ilim 1 b0
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Serial Peripheral Interface (SPI) Table 9.
BIT b0-b7 b0-b7 b0-b7 b0-b7 b0-b7 b0-b7
L9733
Command Register Logic Definition
STATE 0 1 0 1 0 1 STATUS OUT1 - OUT8 are Commanded Off OUT1 - OUT8 are Commanded On OUT1 - OUT8 Diagnostic is No Latch Mode OUT1 - OUT8 Diagnostic is Latch Mode OUT1 - OUT8 Switching OFF Overcurrent Protection OUT1 - OUT8 Linear Overcurrent Protection Writing Mode Output Output Diag Diag Protection Protection
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L9733
Other L9733 Features
6
6.1
Other L9733 Features
Charge Pump Usage
In order to provide low Rdson values when connected in a high side configuration, a charge pump to drive the internal gate voltage(s) above Vbat is implemented. The charge pump used on the L9733 doesn't need external capacitor. The L9733 uses a common charge pump and oscillator for all the 8 configurable output channels. The charge pump uses the Vbat supply connected directly to the Vb pin. The normal range of the Vbat voltage is 10 to 18V18V. However, the L9733 is functional with Vbat voltages as low as 4.5V DC with eventually a degradation of Rdson. The frequency range of this charge pump is from 3.6 to to 7.6 MHz. The frequency is above 1.8MHz in order to be above the AM radio band and below 8.0MHz so that harmonics do not get within the FM radio band.
6.2
Waveshaping
Both the turn on and the turn off slew rates on all outputs (OUT1-8) are limited to between 10s and 100s for both rise and fall times (10 to 90%, and vice versa), to reduce conducted EMC energy in the vehicle's wiring harness. The characteristics of the turn-on and turn-off voltage is linear, with no discontinuities, during the output driver state transition.
6.3
POR Register Initialization
When the L9733 wakes up, the Vdd supply to the L9733 is allowed from 0 to 5 VDC in 0.3 to 3ms. The L9733 has a POR circuit, which monitors the Vdd voltage. When the Vdd voltage reaches an internal threshold, and remains above this trip level for at least 5 to 20s, the Command and Fault registers are "cleared". Before Vdd reaches this trip level, none of the eight outputs are allowed to momentarily glitch on.
6.4
Thermal Shutdown
Each of the eight outputs has independent thermal protection circuitry that disables each output driver once the local N-Channel MOSFET's device temperature reaches between +151 and +200C. A filter is present to validate the thermal fault (5s to 20s). There is a 5 to 15C hysteresis between the enable and disable temperature levels. The faulted channel will periodically turn off and on until the fault condition is cleared, the ambient temperature is decreased sufficiently or the output is commanded off. If a thermal shutdown, of one or more output drivers, is active during the falling edge of the chip select (CS) signal all the bits of the Fault Register are "setted" to "1" (thermal shutdown is not latched and could be read only in the moment it is present). The thermal fault is cleared on the rising edge of Chip Select if a valid DI byte was received.
Note:
Due to the design of the L9733 each output's thermal limit "may not" be truly independent to the extent that if one output is shorted, it may impact the operation of other outputs (due to lateral heating in the die).
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Fault Operation
L9733
7
Fault Operation
The fault diagnostic capability consists of one internal 16 bits shift register and 2 bits are used for each output. The diagnostic information are: no fault present, overcurrent, open load and short circuit. All of the faults will be cleared on the rising edge of Chip Select if a valid DI byte was received
Table 10.
OUT 8 MSB D1 b15 D0 b14
Fault Register Definition
OUT 7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 LSB D1 b13 D0 b12 D1 b11 D0 b10 D1 b9 D0 b8 D1 b7 D0 b6 D1 b5 D0 b4 D1 b3 D0 b2 D1 b1 D0 b0
Table 11.
D1 0 0 1 1
Fault Logic Definition
D0 0 1 0 1 No fault is present Open load Short circuit to GND (low side) or Short circuit to Vbat(high side) Overcurrent FAULT STATUS
If all the bits b0-b15 of the fault register have value '1' it means that a thermal fault, at least on one of the eight independent Outputs, occurred.
7.1
Low Side Configured Output Fault Operation
The diagnostic circuitry verifies for the low side configured output the following condition: Normal operation, open load, short circuit to GND and overcurrent (only if the switching OFF protection, selectable for each channel via SPI bus, is active). The diagnostic circuitry operates in two different modes, selected for each channel by SPI: no latch mode and latch mode. The fault priority is overcurrent and then open load or short circuit to GND, this means that if an overcurrent occurs the fault register is always overwritten and following open load or short to GND faults that happen before that the register is cleared will be ignored.
7.1.1
No latch mode
This diagnostic operating mode doesn't latch open load and short to GND faults. 1. Open load The diagnostic of open load is detected only in OFF condition sensing the Drn1-8 output voltage. This fault is detected on the falling edge of the CS input if the power drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and
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L9733
Fault Operation Vth_GND. An internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected. 2. Short Circuit to GND The diagnostic of short circuit to GND is detected only in OFF condition sensing the Drn1-8 output voltage. This fault is detected on the falling edge of the CS input if the power drain voltage is lower than the Vth_GND threshold. Overcurrent The diagnostic of overcurrent is detected only in ON condition, if the switching OFF protection of the channel is enabled (default), sensing the current level of the output power transistor. If the output current has been above the short threshold Iovc for the filtering time Tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register. There are three possibilities to restart one output after the fault has occourred: - - Automatically after a time Tres On the rising edge of CS if two valid DI byte has been received and first the Output Status in the command register is written with logic '0' and then with a logic "1" in the following SPI cycle On the rising edge (low to high transition) at the corresponding parallel input pin (only for Outputs 6-8). If the switching OFF protection is not active the On phase overcurrent protection is a linear current limitation and no diagnosis is available.
3.
- -
The use of the IN6-8 pins for PWM control on the outputs 6-8 could generates bad diagnostic behavior when the falling edge of CS happens a short time after the falling edge of IN6-8 during the power MOS transient. Software filtering may be needed to ignore fault signals during Drn6-8 transient after falling edge of IN6-8.
7.1.2
Latch mode
This diagnostic operating mode latches all faults when they happen. 1. Open load The diagnostic of open load is detected only in OFF condition sensing the Drn1-8 output voltage. This fault is detected if the power drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and Vth_GND for the filtering time Tfilt. An internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected. Short Circuit to GND The diagnostic of short circuit to GND is detected only in OFF condition sensing the Drn1-8 output voltage. This fault is detected if the power drain voltage is lower than the Vth_GND threshold for the filtering time Tfilt. Overcurrent The diagnostic of overcurrent is detected only in ON condition, if the switching OFF protection of the channel is enabled (default), sensing the current level of the output power transistor. If the output current has been above the short threshold Iovc for the filtering time Tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register. If the switching OFF protection is not active the On
2.
3.
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Fault Operation
L9733 phase overcurrent protection is a linear current limitation and no diagnosis is available. There are three possibilities to restart one output after the fault has occourred: - - Automatically after a time Tres On the rising edge of CS if two valid DI byte has been received and first the Output Status in the command register is written with logic '0' and then with a logic "1" in the following SPI cycle On the rising edge (low to high transition) at the corresponding parallel input pin (only for Outputs 6-8). If the power MOS transient, after a switching-off command, is longer than Tdel filtering time, a bad diagnostic behavior happens and software filtering may be needed.
-
7.2
High Side Configured Output Fault Operation
The diagnostic circuitry verifies for the high side configured output the following condition: Normal operation, open load, short circuit to Vbat and overcurrent (only if the switching OFF protection, selectable for each channel via SPI bus, is active). The diagnostic circuitry operates in two different modes, selected for each channel by SPI: no latch mode and latch mode. The fault priority is overcurrent and then open load or short circuit to Vb, this means that if an overcurrent occurs the fault register is always overwritten and following open load or short to Vbat faults that happen before that the register is cleared will be ignored.
7.2.1
No latch mode
This diagnostic operating mode doesn't latch open load and short to Vbat faults. 1. Open load The diagnostic of open load is detected only in OFF condition sensing the Src1-8 output voltage. This fault is detected on the falling edge of the CS input if the power drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and Vth_GND. An internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected. Short Circuit to Vb The diagnostic of short circuit to Vbat is detected only in OFF condition sensing the Src1-8 output voltage. This fault is detected on the falling edge of the CS input if the power drain voltage is higher than the Vth_Vbat threshold. Overcurrent The diagnostic of overcurrent is detected only in ON condition, if the switching OFF protection of the channel is enabled (default),sensing the current level of the output power transistor. If the output current has been above the short threshold Iovc for the filtering time Tdel the output power is switched off and at the same time an overcurrent
2.
3.
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L9733
Fault Operation fault is written in the fault register. There are three possibilities to restart one output after the fault has occourred: - - Automatically after a time Tres On the rising edge of CS if two valid DI byte has been received and first the Output Status in the command register is written with logic '0' and then with a logic "1" in the following SPI cycle On the rising edge (low to high transition) at the corresponding parallel input pin (only for Outputs 6-8). If the switching OFF protection is not active the On phase overcurrent protection is a linear current limitation and no diagnosis is available. The use of the IN6-8 pins for PWM control on the outputs 6-8 could generates bad diagnostic behavior when the falling edge of CS happens a short time after the falling edge of IN6-8 during the power MOS transient. Software filtering may be needed to ignore fault signals during Drn6-8 transient after falling edge of IN6-8.
- -
7.2.2
Latch mode
This diagnostic operating mode latches all faults when they happen. 1. Open load The diagnostic of open load is detected only in OFF condition sensing the Src1-8 output voltage. This fault is detected if the power drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and Vth_GND for the filtering time Tfilt. An internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected. Short Circuit to Vb The diagnostic of short circuit to Vbat is detected only in OFF condition sensing the Src1-8 output voltage. This fault is detected if the power drain voltage is higher than the Vth_Vbat threshold for the filtering time Tfilt. Overcurrent The diagnostic of overcurrent is detected only in ON condition, if the switching OFF protection of the channel is enabled (default), sensing the current level of the output power transistor. If the output current has been above the short threshold Iovc for the filtering time Tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register. - - Automatically after a time Tres On the rising edge of CS if two valid DI byte has been received and first the Output Status in the command register is written with logic '0' and then with a logic "1" in the following SPI cycle On the rising edge (low to high transition) at the corresponding parallel input pin (only for Outputs 6-8). If the switching OFF protection is not active the On phase overcurrent protection is a linear current limitation and no diagnosis is available.
2.
3.
There are three possibilities to restart one output after the fault has occourred:
-
If the power MOS transient, after a switching-off command, is longer than Tdel filtering time, a bad diagnostic behavior happens and software filtering may be needed.
27/33
Fault Operation Figure 6. L9733 Application schematic
L9733
VDD RES SCLK DI DO CS VDO IN6 IN7 IN8 GND
8 HIGH/LOW SIDE DRIVER
CP VBAT
SPI Control Logic
Registers
DRN[x]
High Side Driver Configuration
SRC[x] DRN[x]
To driver 6 To driver 7 To driver 8
Low Side Driver Configuration
SRC[x]
Figure 7.
L9733 HVAC applicative examples
Vbatt
Control Logic
SPI
SM
SM
SM
SM
Control Logic
SPI
L9733
L9733
Stall sense
4 channels configured to low- and 4 channels
Four flap motors become sequentially driven. Unipolar stepper motor are selected by 4 high-side configured switches. If the decoupling diodes are inside the motor housing, only 8 wires are needed to drive this arrangement.
configured to high side build a quad half bridge. This allows to drive 3 DC-motors in sequential ly.
28/33
VBAT
Vbatt
MM
MM
MM
L9733 Figure 8. L9733 Powertrain applicative examples
Vbatt
Fault Operation
Vbatt
Tach-Out (PWM) Control Logic Control Logic Key-On Relay Power Latch Relay Canister Purge Relay (opt PWM) MIL Lamp Water Lamp Fuel Pump Relay (opt PWM) Coolant Fan Relay SPI
Starter Relay A/C Fan Relay A/C Compressor Relay Air Pump Relay
SPI
SM
Idle Speed Control
L9733
L9733
Main Relays and Lamps Driving
Idle speed stepper motor driving and auxiliary loads
29/33
Package informations
L9733
8
Package informations
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 9. SO28 Mechanical Data & Package Dimensions
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 1.27 16.51 7.6 1.27 0.291 0.016 0.1 0.35 0.23 0.5 45 (typ.) 18.1 10.65 0.697 0.394 0.050 0.65 0.299 0.050 0.713 0.419 mm TYP. MAX. 2.65 0.3 0.49 0.32 0.004 0.014 0.009 0.020 MIN. inch TYP. MAX. 0.104 0.012 0.019 0.013
OUTLINE AND MECHANICAL DATA
SO-28
8 (max.)
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L9733
Package informations Figure 10. PowerSSO28 Mechanical Data & Package Dimensions
DIM. A A2 a1 b c D (1) E (1) e e3 F G G1 H h k L M N O Q S T U X Y MIN. 2.15 2.15 0 0.18 0.23 10.10 7.4 0.65 8.45 2.3 0.10 0.06 10.50 0.40 5 0.55 4.3 10 1.2 0.8 2.9 3.65 1.0 4.2 6.6 4.8 7.2 0.165 0.260 0.047 0.031 0.114 0.144 0.039 0.190 0.283 0.85 0.022 0.169 10 mm TYP. MAX. 2.47 2.40 0.075 0.36 0.32 10.50 7.6 MIN. 0.084 0.084 0 0.007 0.009 0.398 0.291 0.025 0.033 0.090 0.004 0.002 0.413 0.016 5 0.033 inch TYP. MAX. 0.097 0.094 0.003 0.014 0.012 0.413 0.299
OUTLINE AND MECHANICAL DATA
10.10
0.398
(1) "D" and "E" do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0.15 mm per side(0.006")
PowerSSO-28 (exposed-pad)
A2
A
h x 45u
c
G
C
LEAD COMPLANARITY
D e
A a1
Y
O
F
E
H
U
Q BOTTOM VIEW
B
M
0.1 M A B e3
b
S
X
7633868 A
k
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Revision history
L9733
9
Revision history
Table 12.
Date 13-Apr-2005 15-Jun-2006 08-Aug-06
Document revision history
Revision 1 2 3 Initial release. Changed only look and fill. Modified Table 8: Bit Command Register Definition on page 21 Changes
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L9733
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